Education:
BSEE from UT Knoxville, Magna Cum Laude (May
1999)
MSEE from UT Knoxville (May 2001)
Thesis Title:
A PLL Frequency Synthesizer For A High Temperature Transceiver Realized In 0.5um
SOS Technology (PDF version
available)
Thesis Advisor:
Dr. Jim Rochelle
Assistantship:
UT Graduate Research Assistant (GRA)
Research conducted at the Oak Ridge National Laboratory
Fellowship:
Lucent Fellowship in the UT/ORNL Joint Program
Employer:
Siemens
Molecular Imaging
Prior Employment:
Analysis and Measurement Services Corporation
Flextronics Semiconductor (formerly ASIC International)
Interests:
Analog, digital, and mixed-signal circuit design
Signal analysis
ASIC design
Programming
Wireless systems
Hobbies:
Snow skiing, rock climbing, playing the bass guitar, watching the Vols...
E-Mail:
amoor@utk.edu
| Thesis chip: | RF_CHIP_1 (GIF) |
| Voltage-controlled oscillator: | VCO (GIF) |
| Programmable frequency divider: | DIVIDER (GIF) |
HW 1 - tutor1.spice (Two-transistor inverting
amplifier) AC analysis
HW 2 - Datapath layout My partner for the final project in this class was Aaron Symko.
HW 1 - tutor1.spice transient analysis
HW 1 - tutor2.spice (Two-transistor CMOS current
mirror) DC analysis
HW 2 - tutor3.spice (9-transistor CMOS
operational amplifier) ac analysis - part 1
HW 2 - tutor3.spice ac analysis - part 2
HW 2 - tutor3.spice dc analysis
HW 2 - tutor4.spice (switched capacitor filter
circuit) transient analysis
HW 2 - tutor5.spice (ring oscillator) transient analysis
HW 2 - tutor6.spice (4-bit DAC without buffer) transient analysis
EE 651 Homework Links
HW 3 - IRSIM simulation
HW 4 - Timing report
HW 4 - Part A (no load)
HW 4 - Part B (single load) zoomed in
HW 4 - Part B (single load) full
HW 4 - Part C (single load w/1000u M2) zoomed in
HW 4 - Part C (single load w/1000u M2) full
HW 4 - Part D (single load w/1000u M1) zoomed in
HW 4 - Part D (single load w/1000u M1) full
HW 4 - Part E (single load w/1000u poly) zoomed in
HW 4 - Part E (single load w/1000u poly) full
HW 4 - Part F (single load w/1000u ndiff) zoomed in
HW 4 - Part F (single load w/1000u ndiff) full
HW 5 - SPICE simulation
HW 5 - Part B (before PFET optimization)
HW 5 - Part B (after PFET optimization)
HW 6 - Standard-height layout
HW 6 - Summary report
HW 7 - AOI Schematic (SUE)
HW 7 - AOI Pre-layout simulation (IRSIM)
HW 7 - AOI Layout (MAX)
HW 7 - AOI Post-layout simulation (IRSIM)
HW 8 - Design considerations for 2-input AND and 3-input AND
HW 8 - 2-input AND Schematic (SUE)
HW 8 - 2-input AND Pre-layout simulation (IRSIM)
HW 8 - 2-input AND Layout (MAX)
HW 8 - 2-input AND Post-layout simulation (IRSIM)
HW 8 - 3-input AND Schematic (SUE)
HW 8 - 3-input AND Pre-layout simulation (IRSIM)
HW 8 - 3-input AND Layout (MAX)
HW 8 - 3-input AND Post-layout simulation (IRSIM)
HW 8 - 4-input AND: See Aaron Symko's web site
Project - Non-inverting 2-input multiplexer simulation
FET-level schematic
Truth table
Datapath Cell Layout
Datapath Cell Simulation (no load)
Datapath Cell Simulation (4-bit parallel array)
Standard Cell Layout
Standard Cell Simulation (no load)
Standard Cell SPICE Simulation (no load)
Summary of Datapath and Standard Cell Simulation Results (with loading)
Final Project Report"
Revised SMART FRAME layout
EE 552 Homework Links
EE 551 Project Information
Our project was a Differential Score-Keeping System.
