Adaptive computing systems (ACSs) can serve as flexible hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take months for a hardware engineer to develop and debug. To enable application designers to map their applications automatically onto ACSs, a software design environment called CHAMPION was developed at the University of Tennessee. This environment permits high-level design entry using the Cantata graphical programming environment from KRI and hides from the user the low-level details of the hardware architecture.

The key idea underlying CHAMPION is its ability to reuse pre-compiled hardware modules written in VHDL. These modules produce identical results to fixed-point C modules installed in Cantata which the user interconnects graphically and simulates on a general purpose UNIX workstation. The resulting net-list is converted into a directed graph and manipulated by CHAMPION so that data widths and clock delays are matched. If the graph is too large for a single FPGA, then it is partitioned automatically.

To benchmark CHAMPION, an automatic target recognition application containing 93 modules interconnected by 226 nets was captured using Cantata. Mapping the net-list onto a Wildforce ACS containing 5 FPGAs required 6 staff-weeks to map manually while CHAMPION was able to perform the mapping in less than 6 minutes. Thus, a productivity gain of over 2000 was demonstrated.

Additional validation of CHAMPION was performed using three other moderately complex applications. These were mapped to the Wildforce as well as the Wildcard and SLAAC- 1V ACS platforms. All of these applications were also mapped into single-chip ASICs (0.5- micron CMOS).

Thus, CHAMPION enables application development to be accomplished in less time and ACSs to be utilized by a wider audience. Furthermore, CHAMPION provides the means to map onto multiple ACS platforms and ASICs, thereby exploiting rapid advances being made in hardware.

Publications:

Final Report (671 KByte pdf; 31 color pages)

Overview Slides (1.4 MByte pdf; 28 color pages)

FCCM-01 Slides (557 KByte pdf; 15 color pages)

FCCM-01 Paper (166 KByte pdf; 11 b/w pages)

HPEC-00 Paper (37 KByte pdf; 3 b/w pages)

MAPLD-99 Paper (72 KByte pdf; 7 b/w pages)

FCCM-99 Paper (31 KByte pdf; 2 b/w pages)

Srijanto M.S. (1.7 MByte pdf; 141 mostly b/w but some color pages)

Ong Ph.D. (3.8 MByte pdf; 188 mostly b/w but some color pages)

Kerkiz Ph.D. (0.4 MByte pdf; 143 b/w pages)

Levine M.S. (0.4 MByte pdf; 99 b/w pages)

Natarajan M.S. (0.6 MByte pdf; 97 b/w pages)

Shetters M.S. (0.4 MByte pdf; 56 b/w pages)