Homework_5 -- Developing, Verifying and Installing DesignWare

Written by F. Karakaya and D. Bouldin on 3/12/02 and updated on 1/28/04

Objective

The objective of this tutorial is to learn how to develop, verify and install new Synopsys DesignWare components.
The circuit to be implemented computes the dotproduct of two vectors.
For example, for three dimensions,

Thus, the dotproduct function can be implemented using existing DesignWare components (multipler, adder and counter).

Fixed-point arithmetic

It is common for hardware arithmetic functions to  be  calculated
using  fixed-point  representation whereas software arithmetic is
often performed using floating-point.  Fixed-point representation
has  "int"  bits  to  the  left of the binary point  and  "fract"
bits for the fractional part to the right of  the  binary  point.
When  fract=0, the number is considered an integer.  For example,
if the two inputs to a multiplier are both 16 bits  with   int=10
and  fract=6,   the   resulting   addition   would   require   33
bits [2(int + fract)+1].  To maintain  the  fractional  precision
of  fract=6,    the 33-bit  result should be shifted to the right
by  6  bits.   This  is  equivalent  to  truncating   the   least
significant   6  bits   or   just   not wiring  them to the final
output.  Hence, the topmost 10 bits and the next 6 bits (total of
16 bits)  would  be connected  to  the output.

Let's assume we have two numbers :

                binary   decimal
                ------   -------
                10.01 = -1.75
                01.01 =  1.25

If we multiply these in decimal:    -1.75  X  1.25  =     -2.1875

To perform the multiplication in binary, we see the first  number
is  in  2's  complement  form  and  is  negative.  So, we have to
convert this negative number to its positive form:

		decimal   -->   binary                   
		-------         ------ 
		1.75      -->   01.11

Now when we multiply:

              0111
              0101
           x
           ------------
             0 1 1 1
           0 0 0 0
         0 1 1 1
       0 0 0 0
   +
   ------------------
     0 0 1 0 0 0 1 1 =>  0010.0011 = 2.1875

But we know that the result is negative so we convert it back  to
2s complement form:

    1 1 0 1 1 1 0 1  => 1101.1101 = -2.1875

      binary   --> decimal
      ---------   --------
      1101.1101 = -2.1875

Verification

When developing a VHDL implementation, we always verify its operation using pre-synthesis and post-layout simulations. In order to know that the VHDL simulation responses are correct, we can implement a fixed-point C version of the desired circuit and subject it to the same stimuli as the VHDL circuit as depicted in the flowchart below:

PART A: SIMULATIONS USING MATLAB, C AND VHDL

Tutorial Files and Data Preparation

The tutorial files may be copied by typing:
cp -r /usr/cad/course/designware/dotproduct hw5
cd hw5
The files contain the C and VHDL to calculate the dotproduct of two seven-dimensional vectors using fixed-point arithmetic
with int=10 and fract=6 (total of 16 input bits each). Stimuli containing nine sets of data for the two vectors are provided in binary format: bin1 and bin2

For the dotproduct, we multiply two 10.6 numbers to get 21.12
which we truncate to 21.6.  We then add this to another 21.6
and get a 22.6.  Then we add this  to  another  21.6 and get a 23.6.

The input data provides 9 sets of 7-dimensional data:

  a1*b1 + a2*b2 + a3*b3 + a4*b4 + a5*b5 + a6*b6 + a7*b7

First data set of 7 numbers:

vector1
---------
a1 =  470.71875
a2 =  407.234375
a3 = -472.625
a4 = -343.609375
a5 =  461.890625
a6 =  319.21875
a7 = -507.8125

vector2
---------
b1 =  - 41.28125
b2 =  -104.765625
b3 =    39.375
b4 =  - 87.609375
b5 =  -178.109375
b6 =   511.21875
b7 =  -387.8125

dotproduct = a1*b1 + a2*b2 + a3*b3 + a4*b4 + a5*b5 + a6*b6 + a7*b7

So,

  matlab/out.txt = flop/out_dotpro = 227257.365967

  fxp/out_dotpro = dec_vhdlout     = 227257.359375

The above is repeated 9 times.

The 64th line is all zeros to serve as a delimiter.

Matlab Simulation

cp dec1 matlab/in1.txt
cp dec2 matlab/in2.txt
cd matlab
View the contents of dotpro.m
matlab
In the Matlab command window, type:
dotpro
exit
To the UNIX prompt, type:
more out.txt

C Simulations

Now, move to the floating-point C subdirectory:
cd ../systemC/flop
Here you will find C files which implement the dotproduct function and read in a source (stimuli) and write out a sink (output responses).
To compile, just type:
make -f Makefile.gcc
This will take about two minutes. Then, type:
run.x
Now the file "out_dotpro" contains the results in floating-point, decimal format.

Now, move over to the fixed-point C subdirectory:
cd ../fxp
To compile, just type:
make -f Makefile.gcc
This will take about five minutes. Then, type:
run.x
Now the file "out_dotpro" contains the results in fixed-point, decimal format.

VHDL Pre-synthesis Simulation---Error needs to be fixed--D. Bouldin 3/22/07

Check dataout.txt which contains nine 29-bit numbers. The result of the dot-product operation has already been truncated by 6 bits to preserve our fixed-point representation. To convert dataout.txt to decimal, edit the bin2dec PERL script for the filename "dataout.txt" and type:
bin2dec 23 > dec_vhdlout
This will convert the 29-bit number (with int=23 and fract=6) to decimal.

Now compare the sets of responses:

COMMAND SUMMARY:

cp -r /usr/cad/course/designware/dotproduct hw5
cd hw5
bin2dec 10 > dec2  
vi bin2dec  bin1
bin2dec 10 > dec1
cp dec1 systemC/fxp/vector1
cp dec1 systemC/flop/vector1
cp dec2 systemC/fxp/vector2
cp dec2 systemC/flop/vector2
cp dec1 matlab/in1.txt
cp dec2 matlab/in2.txt
cd matlab
matlab 
In the Matlab command window, type:
dotpro
exit
more out.txt
cd ../systemC/flop
make -f Makefile.gcc
run.x
more out_dotpro
cd ../fxp
make -f Makefile.gcc
run.x
more out_dotpro
cd ../../vhdl
modifier 16 7 6 > TOP_16.vhd
cd ..
scriptmodelsim
more dataout.txt
vi bin2dec  dataout.txt
bin2dec 23 > dec_vhdlout
more dec_vhdlout

ASIC FLOW

PART B: POST-LAYOUT SIMULATION (skip Spr 2007)

Now follow the steps in homework_3 to synthesize and place/route the dotproduct function targeting the TSMC-0.18 process. Perform post-layout simulation using ModelSim and the stimuli in Part A and compare your results with the pre-synthesis simulation results.

PART C: INSTALLING YOUR OWN DESIGNWARE (skip Spr 2007)

To install some of your own VHDL modules for future reuse, you must first create a synthetic library description,
then synthesize your modules and store the results in the appropriate database format.
Move to your own hw5 directory and note the contents of TEST_DW_SL.sl which has been provided for you.
Now, type:
mkdir TEST_DW
cd TEST_DW
mkdir vhdl
cp ../vhdl/latch.vhd vhdl
cp ../vhdl/acumulator.vhd vhdl
cd ..; synopsys_tools; dc_shell

WITHIN DC_SHELL:
define_design_lib TEST_DW -path ./TEST_DW
analyze -f vhdl -lib TEST_DW { ./vhdl/latch.vhd ./vhdl/acumulator.vhd }
report_design_lib TEST_DW
read_lib TEST_DW_SL.sl
write_lib TEST_DW_SL.sldb
report_synlib TEST_DW_SL.sldb
exit

When you want to reuse your latch and acumulator modules, just write the appropriate VHDL module and "map" to TEST_DW.
cd vhdl
cp TOP.vhd HW5C.vhd

Edit HW5C.vhd to include invoke your DW (latch and acumulator) cd ..

Edit .synopsys_dc.setup to add pointers to your TEST_DW:
synthetic_library=synthetic_library+TEST_DW_SL.sldb
link_library=link_library+TEST_DW_SL.sldb
Edit scriptmodelsim to include a map to your DW and to compile HW5C.vhd
Execute scriptmodelsim and capture the appropriate simulation waveforms.

Link your results to your restricted webpage.

Update /usr/cad/public_html/552hw_status.html