Homework_2: Custom Cell Layout

Simple Rules            lambda
----------------------- ------
1. min. width of active = 10
2. min. width of poly   =  2
3. min. poly extension  =  2
4. min. wire separation =  4
5. min. width of metal  =  4
6. contacts are 4x4

Note: active surrounded by n-select --> ndiff
      active surrounded by p-select --> pdiff

Wiring can be facilitated using "Create Path". Metal paths are generally 4-lambda (1.2-micron) wide.
It may be helpful to copy an existing (read-only) standard cell into your layout temporarily
and copy vias, etc into your design. To do this, use "Create Instance" and access "OSU_AMI06 --> INVX1 --> layout"
and select "Edit --> hierarchy flatten".
Edit the generated layout until it resembles the original one and then delete the example cell.
Then perform the extraction, LVS, DRC,
and repeat the Verilog-XL and Spectre simulations.


Remove any existing pins and create new ones; otherwise, LVS may trigger a mismatch.
When you click on "create ---> pins" a box will pop-up for you to supply "pin-name".
At the bottom, select "Access direction" and disable everthing except "Left and Right"
for VDD and GND and "Top and Bottom" for inputs and outputs.

Metal-2 rules dictate the horizontal spacing of 1.6u or 8-lambda
while metal-1 rules dictate the vertical spacing of 2.0u or 10-lambda.

Using a grid permits the cell boundaries to overlap horizontally by 4.8u (16-lambda).

Note: The grid layer is "hilite d3" (LSW-->Edit-->Set Valid Layers).

Metal-1 pins must fall on the Metal-2 grid line and preferably at a grid intersection.

Metal-2 pins must fall on the Metal-1 grid line and preferably at a grid intersection.





The vertical overlap of the cell boundaries is 4.8u (vdd) or 2.4u (gnd):



Note how the individual cell grids overlap horizontally by (4-lambda) and vertically by (5-lambda):