Part A: Automatic Leafcell Generation Using ProGenesis
This homework involves automatic leafcell generation using ProGenesis.
In general, we begin by drawing a schematic and performing the
pre-layout simulation with Spectre.
In our case, we already have the schematic for "inv" in the AMI library
which has been simulated successfully using Spectre.
So, we first copy the following directories/files:
cp -r /usr/cad/course/prolific hw8
cd hw8
You should now have the following:
MUX2.sp
cmds
inv.sp
stream.map
streamin_prolific.tmpl
togds
tech/ami.db
tech/progen.tcl
tech/proview.tcl
In general, you must edit the Spectre net-list to use
"TN" for nfets and "TP" for pfets as preferred by the
Prolific tools:
m1 vss in out vss TN w=3.0u l=0.6u
m2 vdd in out vdd TP w=7.5u l=0.6u
Another example is shown for NAND2X1Next, set the tool environment: prolific_tools Then, convert the Spectre net-list into Prolific's internal "cel" format: prospin -l inv inv.sp Next, we will invoke the Prolific leafcell generator to layout this schematic using a process-dependent tech-file that includes the SCMOS_SUBME (lambda=0.2) design rules along with constraints. This produces a layout which conforms to the 100-lambda standard- height cell format for the AMI035 process: progen -t tech/ami.db -i inv.cel -o inv.agd -g Alternatively, you can omit the "-g" option and then type: proview -t tech/proview.tcl inv.agd which allows you to view the final "inv" result. "cmds" contains the following commands: prospin -l inv inv.sp progen -t tech/ami.db -i inv.cel -o inv.agd -g proview -t tech/proview.tcl inv.agd togds inv Once the layout is produced in the Prolific format (agd), we can convert it to gds and strip off any unnecessary labels by typing: togds inv ---2006: skip this section Now, set the tool environment for Cadence tools and invoke Virtuoso: cadence_tools icfb& Create the library (hw8) first. Then attach the techfile (File-->attach techfile). See: create-hw8 Import the gds file using "stream.map" and "streamin_prolific.tmpl" by following these steps: In the icfb log window, select "File" --> "Import" --> "Stream". In the "Stream In" form, type: streamin_prolific.tmpl Click load. Replace the content of the "Input File", "Top Cell Name", and "Library Name" with the name of the gds2 file (inv.gds), the top design (inv), and the Library (hw8) where you want the design to be, respectively and click ok. See: streamin In the Library-Manager window, select "refresh" and then double-click on "layout". Next, perform a DRC check and then extract the result and perform the post-layout simulation. Repeat the above for "MUX2.sp": --------- Note "cmds" also contains the following commands: prospin -l mux2 MUX2.sp progen -t tech/ami.db -i mux2.cel -o mux2.agd > vlsi6-mux2.log grep Proc vlsi6-mux2.log proview -t tech/proview.tcl mux2.agd togds mux2 You can view the final "mux2" result. Note that the mux2 takes only 1 min 16 secs on vlsi6 but takes 3 mins 29 secs on vlsi2. Convert the agd format to gds and import into Virtuoso. View the "layout". Perform a DRC check, extraction and post-layout simulation. Capture the appropriate screens and edit the Homework Status webpage. Note: To perform transistor folding using Prolific, just include the "-f" option:
prospin -f -l inv inv.sp A layout w/o folding may be too high while one with folding is okay. When using Virtuoso/Layout-XL and "generate from source", you can select the folding option.
Prolific-Overview (restricted pdf).
Prolific-Comparisons-Project (restricted pdf).
Part B: Comparison of two automatically generated layouts
The part consists of repeating hw6 and hw8 for a single design and comparing their results. You do NOT need to do a manual layout. Manual vs. Auto Comparisons (restricted pdf).
Use existing cells and schematics in the OSU_AMI06 library
to develop a macro which incorporates a mixture
of the cell groups listed below using:
at least two instances each of both cells from group-a,
at least two cells from group-b,
at least two cells from group-c and
Thus, the total complexity should range between 20W and 30W.
W---Cell
--------
group-a:
3--NAND2
3--NOR2
group-b:
4--AND2
4--AOI21
4--NAND3
4--OAI21
4--OR2
group-c:
6--MUX2
7--XNOR2
7--XOR2
8--NOR3
PartB Schematics:
Post your schematic at:
/home/username/public_html/hw8b.gif
Previous schematics when the complexity was at least 44W
(you may use one of these without the HA or FA):
ndennisdarren
sfields1
gilbert
robertg
jjeon
nmichou
jpendlet
ishaik
vprasad
jwhite25
Compose your schematic at both the cell-level and fet-level. Determine the truth table for your macro but do not optimize it. Perform pre-layout VerilogXL simulation (can skip this). Perform pre-layout Spectre simulation. Generate two standard-height layouts that are compatible with the OSU_AMI06 library: (a) auto-cell using SOC_Encounter (like hw6) (b) auto-fet using progen (like hw8a) For Fall 2006, display the two layouts on your restricted webpage and list the sizes and stop here. ========== DB needs to fix tech/ami.db in order to proceed w/o DRC errors: Use Virtuoso to read in each DEF file, add pins for gnd! and vdd! (Notes: Skip to page 4 and in the command window, perform "Import-def". (On page 7, replace "Replace-All" with "Apply, then Replace-All".) For each layout, perform DRC and LVS and post-layout Spectre simulation. Optional: Add shaping inverters and 4 load-chains (like hw4) to both layouts and perform post-layout Spectre simulation with shaping/loading. Make a table comparing the layouts in terms of area (W horizontal grids) and delay (fan-out-4) but don't count the area/delay of the shaping/loading. Compare the quality of the results and the design time required for these methods. All of the layouts should be the same height. If Progen does not give you the 30-micron height, then use the -f or folding option (or manually split the offending fets in filename.sp). Progenesis does NOT use logic simplification and you should not either. All of the layouts should conform to the grid and be an integer multiple of 8-lambda (1.6u) in width.