Rules for Standard-height Cells
WARNING: DO NOT NAME YOUR STDCELLS AND FLINTCELLS WITH THE SAME NAME.
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Basic standard cell format
(Originated by L. Clonts and revised by D. Bouldin on 10/2/92)
(Revised again on 11/16/99 by C. Ku)
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|<3><2><------- Distance = 8(N)+4, N = 1,2,**. ------><2><3>|
-|-----------------------------------------------------------|-
| NWELL |
| NWELL |
5| NWELL |5
| NWELL |
| NWELL |
_| |_
|___################ ~//~ ################ |
| ################ ~//~ ################ |
| ################ ~//~ ################ |
8| ################ Vdd! ~//~ Vdd! ################ |8
| ################ metal1 ~//~ metal1 ################ |
| ################ ~//~ ################ |
| ################ ~//~ ################ |
_| ################ ~//~ ################ |_
| | | | | |
| | | | | |
| | | | | |
| | | | | |
28| | | PMOS transistors | | |28
| | | | | |
| | | | | |
| __****____****____ ~//~ ____****____****__ |
_| __****____****____ ~//~ ____****____****__ |_
| __****____****____ ~//~ ____****____****__ |
| __****____****____ ~//~ ____****____****__ |
| |------ Distance = 8(N), N = 1,2,**. --------| |
| | | | | |
| | | | | |
| | | | | |
22| | | NMOS transistors | | |22
| | | | | |
| | | | | |
| | | | | |
| | | | | |
_| | | | | |_
| ################ ~//~ ################ |
| ################ ~//~ ################ |
| ################ ~//~ ################ |
8| ################ GND! ~//~ GND! ################ |8
| ################ metal1 ~//~ metal1 ################ |
| ################ ~//~ ################ |
| ################ ~//~ ################ |
_| ################ ~//~ ################ |_
| PWELL |
| PWELL |
5| PWELL |5
| PWELL |
| PWELL |
-|-----------------------------------------------------------|-
(-3,-2) |<3><2><-------- Distance = 8(N)+4, N = 1,2,**. -----><2><3>|
## = Metal_1
** = VIA
Notes:
1) All I/O terminals must be vias on the indicated **** positions
which fall on a horizontal grid of 8 lambda. This permits the
STDCELL router to connect a Metal_2 wire of width 4 to the via
and a guarantee that the spacing between Metal_2 wires in adjacent
grids meets the required minimum of 4 lambda.
If vias or Metal_2 do not completely fill the **** locations, the
STDCELL router may use these locations as feed throughs for over-
the-cell routing. On occasion, it is okay to block one of these
grids if there are sufficient grids available (e.g. dfbf311).
2) The wells must be as indicated on the sides of the cell. However,
the center of the design can have the NMOS and PMOS transistor
in any configuration so long as no DRC errors occur in the spacing.
3) The Vdd and GND supply must labeled as Vdd! and GND!.
4) The final cell must have the left-bottom corner positioned at grid
location (-3,-2).
5) Any plugs on the sides of the cells must be in the top 4 lambda of the
Vdd! lines and in the bottom 4 lambda of the GND! lines. In addition,
the plugs must be positioned directly at the start of the supply lines.
That is, plugs must be at least 4 lambda from the edge to supply lines
to prevent DRC errors with other cells.
dbouldin@utk.edu