Cadence Design Systems at the University of Tennessee
Overview
The Electrical & Computer Engineering Department at
the University of Tennessee is a participant in
Cadence Design Systems' university program which is
designed to facilitate the use of Cadence Design Systems tools by undergraduate and
graduate students in engineering courses and in academic research.
Retail Value
Faculty Contact
System Administration Contact
Curriculum Using Cadence Design Systems Software:
- ECE 552
- Students in this graduate course use the System Level Design Bundle
to enter designs using SPW (Signal Processing Workbench). They also
use the Deep Submicron Design Bundle to perform automatic place and route of standard cells using Silicon Ensemble.
- ECE 599
- Students in this graduate course use the Design and Verification Bundle
to enter simulate VHDL and Verilog designs using the NC Simulator.
- ECE 651
- Students in this graduate course use the Custom Integrated Circuits Bundle
to enter designs as a schematic using Composer and simulate using Verilog-XL and/or Spectre.
They then use Virtuoso to perform the layout, followed by DRC and extraction for post-layout simulation.
The resulting designs are submitted to MOSIS for fabrication and subsequent testing.
- ECE 652
- Students in this graduate course use the Deep Submicron Design Bundle
to perform automatic place and route of standard cells using Silicon Ensemble.
They also use the PCB Systems Bundle to perform place and route of printed wiring boards or MCMs.
Research Projects Using Cadence Design Systems Software
- Datapath-Driven IC Design
- Silicon Ensemble is used to perform placement and routing of TMSC standard cells.
For additional information, click
here.
Tutorials and Lab Exercises
For additional information, click here.
Cadence University Program
US Universities Using Cadence
Cadence Newsletters
Updated - May 15, 2006
dbouldin@utk.edu
