DESIGN FOR PACKAGEABILITY
University of Tennessee
Microelectronic Systems Research Laboratory
DESIGN FOR PACKAGEABILITY
OBJECTIVE:
Conventional approaches to microelectronic system design,
partitioning and physical IC design should be optimized to take full
advantage of MCM packaging. The purpose of this project is to
assist the system designer in exploring the design space in order
to perform this optimization. This goal will be accomplished by
identifying the areas of the design cycle which benefit the most
by taking full advantage of the new opportunities which MCMs provide.
Overview Paper (InterPack-95)
APPROACH:
The following design space exploration tools and demonstrations
are planned:
* Design-for-Packageability Tool:
This tool allows the system designer
to explore IC and package options at an early stage of the design
which may be input at different levels of abstractions including
conceptual, behavioral and structural representations.
It will partition a design at different levels of abstractions.
It differs from other partitioning tools in that it considers salient
features of the chosen MCM technology.
* Multi-objective Design Advisor: This information management
tool empowers the designer with an efficient way of filtering and
visualizing results graphically, permitting
trade-off studies to be performed.
* Coordinated IC and MCM Physical Design Tool:
This interactive tool will enable the system designer to consider
the placement of the ICs on the MCM substrate before completing the
IC pin assignment and physical design.
* Application of Design for Packageability:
The tools described
above are being utilized to analyze and partition an
industrial-strength system (SUN MicroSparc CPU) into multiple ICs
that will be fabricated and tested as a single MCM.
ACCOMPLISHMENTS:
The Design-for-Packageability Tool is now in place and has been
used to analyze the SUN MicroSparc CPU. Our results, which were
presented at the 1995 IEEE Multi-Chip Module Conference,
indicated that it is seven times more cost-effective to fabricate
three smaller dies with area-array bonding on an MCM-D substrate
than to produce one large monolithic die.
The optimization
tool selected the best partition from over 21,000 candidates
that were obtained by combining nine functional units
(Memory Management Unit, Floating Point Unit, etc.)
in all possible combinations.
The multi-objective design advisor (MODA) is operational
and can be used to evaluate candidate designs and perform trade-off
analysis. It can also filter a large number of designs and
present them to the designer in rank order using a variety
of criteria.
PLANS:
(1) Synthesize and fabricate via MOSIS the optimum set of MicroSparc CPU
dies using area array pads as determined by our newly developed
Design-For-Packageability (DFP) tool.
(2) Develop an automated means of coordinating IC and MCM physical design
to achieve a global optimum.
(3) Design and fabricate several MCMs via MIDAS.
(4) Utilize our Design-For-Packageability (DFP) tool to
consider other CPU and cache scenarious which affect machine architecture
and hence performance, power, cost, etc.
(5) Extend the capabilities of the DFP tool to permit partitioning
at the behaviorial and structural levels, thereby calibrating the
results obtained at the functional level.
(6) Empower system designers with these system design space exploration
tools via short courses and software releases.
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more information...
DARPA Project Main Page
dbouldin@utk.edu