Adam Miller

  • Anticipated Graduation Term: Summer 2003 MS
  • Interests: VLSI Technology, ASIC Design, Image Processing, Digital System Design
  • Hobbies: Miniatures Gaming, Reading, Everquest.
  • Address: 141 Manor Way Apt. J, Louisville, TN 37777
  • E-Mail: amille10@utk.edu
  • Telephone: (865) 982-4186
  • Employment: Currently a Graduate Research Assistant in ht Microelectronic Systems Group.
  • Thesis Defense Slides
  • Resume
  • Project Report, 551
  • Project Presentation, 551
  • Project Report, 552
  • Presentation for 652 on April 8th, 2003

    ECE651

    Homework 2:
  • Inverter Layout
  • Inverter Extracted
  • Logic Simulation with Verilog XL
  • Extracted Simulation with Spectre

    Homework 3:
  • Adder Slice Schematic
  • Adder Slice Layout
  • Logic Simulation Of Single Bit Adder
  • Layout Simulation Of Single Bit Adder
  • 8 Bit Adder Schematic
  • 8 Bit Adder Layout
  • Logic Simulation Of 8 Bit Adder
  • Layout Simulation Of 8 Bit Adder

    Homework 4:
  • Logic simulations are the same as the logic simulation of the 8 bit adder in homework 3.
  • 8 bit adder with no load
  • 8 bit adder with 1 load
  • 8 bit adder with 4 loads
  • 8 bit adder with 8 loads
  • 8 bit adder with 1 load interconnected with 100-micron metal-1 wire (4-microns wide)
  • 8 bit adder with 1 load interconnected with 100-micron poly wire (4-microns wide)
  • 8 bit adder followed by a 2x buffer with 8 loads to achieve the same delay as case 3
  • 8 bit adder with larger internal W's to achieve the same delay as case 3

    Homework 5:
  • Schematic
  • Layout
  • Logic Simulation
  • Layout Simulation

    Homework 6:

    Part One: BUF1 standard cell
  • Symbol (54 lambda)
  • Schematic (54 lambda)
  • Layout (54 lambda)
  • Pre-Layout Simulation (54 lambda)
  • Post Extraction Simulation (54 lambda)
  • Symbol (66 lambda)
  • Schematic (66 lambda)
  • Layout (66 lambda)
  • Pre-Layout Simulation (66 lambda)
  • Post Extraction Simulation (66 lambda)

    Part Two: 2 to 4 decoder standard cell
  • Symbol
  • Schematic
  • Layout
  • Logic Simulation
  • Layout Simulation

    Part Three: down1/up1 dpp cell, with pfet w equal to 2.5 times nfet w
  • Magic layout of down1
  • Magic layout of up1
  • Symbol of down1
  • Schematic of down1
  • Layout of down1
  • Logic simulation of down1
  • Layout simulation of down1
  • Symbol of up1
  • Schematic of up1
  • Layout of up1
  • Logic simulation of up1
  • Layout simulation of up1

    ECE652

    Homework 1:
  • 2 most critical paths
  • Initial quant_mpy Block
  • qchip Block
  • Rounder Block
  • Rounder Floorplan

    Homework 2:
  • AM2910 Delay Paths
  • AM2910 Square Layout
  • AM2910 Tall Layout
  • AM2910 Wide Layout
  • AM2910 Wide Layout, cells visible

    Simulated Annealing Presentation
  • Slides (PPT)
  • Standard Cell Placement Demo
  • Block Placement Demo