--*************************************************************************
-- HDL Model : ALARM_BLOCK.vhd
-- Original HDL Model : /tnfs/v3/amoor/hw1/behv/alarm_block.vhd
--*************************************************************************
-- Authors and Owners : Synopsys
-- Functional Description : This is a higher-level block that connects various components 
-- of the alarm module.
-- Application Intent : Alarm Clock
-- Interface Specifications :  4 single-bit inputs, 2 buffered integer I/O, 1 buffered bit
-- I/O.
-- Tools and Versions Used/Needed :
---- Altera Version 9.4 Synthesized: Yes
---- Altera Version number Simulated: No
---- Viewlogic Synthesized : Yes
---- FPGA Express Synthesized : No
-- Size :
---- Altera : Logic Cells= 36
----          Input Lines= 4
----          Output Lines= 11
---- Viewlogic : Cell Count= 
----             Gate Equivalent= 
----             Number of Nets= 
--*************************************************************************
--*************************************************************************
entity ALARM_BLOCK is
	port (ALARM,HRS,MINS,CLK: in BIT;
	      CONNECT9:buffer INTEGER range 1 to 12;
	      CONNECT10: buffer INTEGER range 0 to 59;
	      CONNECT11: buffer BIT);
end;

architecture BEHAVIOR of ALARM_BLOCK is

	component ALARM_STATE_MACHINE
	port(ALARM_BUTTON: in BIT;
	     HOURS_BUTTON: in BIT;
	     MINUTES_BUTTON: in BIT;
	     CLK:in BIT;
	     HOURS: out BIT;
	     MINS: out BIT);
	end component;

	component ALARM_COUNTER
	port (HOURS: in BIT;
	      MINS: in BIT;
 	      CLK: in BIT;
	      HOURS_OUT: buffer INTEGER range 0 to 12;
	      MINUTES_OUT: buffer INTEGER range 0 to 59;
	      AM_PM_OUT: buffer BIT);
	end component;

--  Top level nets that connect major modules

	signal CONNECT1,CONNECT2 : BIT;

	begin
 		U1: ALARM_STATE_MACHINE port map (ALARM,HRS,MINS,CLK,CONNECT1,CONNECT2);
		U2: ALARM_COUNTER port map (CONNECT1,CONNECT2,CLK,CONNECT9,CONNECT10,CONNECT11);
end;