--*************************************************************************
-- HDL Model : ALARM_COUNTER.vhd
-- Original HDL Model : /tnfs/v3/amoor/hw1/behv/alarm_counter.vhd
--*************************************************************************
-- Authors and Owners : Synopsys
-- Functional Description : This block is used to set the alarm time.
-- Application Intent : Alarm Clock
-- Interface Specifications : 3 single-bit inputs, 2 buffered integer I/O, 1 buffered 
-- single-bit I/O.
-- Tools and Versions Used/Needed :
---- Altera Version 9.4 Synthesized: Yes
---- Altera Version number Simulated: No
---- Viewlogic Synthesized : Yes
---- FPGA Express Synthesized : No
-- Size :
---- Altera : Logic Cells= 30
----          Input Lines= 3
----          Output Lines= 11
---- Viewlogic : Cell Count= 
----             Gate Equivalent= 
----             Number of Nets= 
--*************************************************************************
--*************************************************************************
entity ALARM_COUNTER is
    port (HOURS, MINS, CLK : in BIT;
	  HOURS_OUT : buffer INTEGER range 1 to 12 := 12;
	  MINUTES_OUT : buffer INTEGER range 0 to 59 := 0;
	  AM_PM_OUT: buffer BIT:= '0');
end;

architecture BEHAVIOR of ALARM_COUNTER is
begin

   process
   begin
     wait until CLK'event and CLK = '1';

	MINUTES_OUT <= MINUTES_OUT;
	HOURS_OUT <= HOURS_OUT;
	AM_PM_OUT <= AM_PM_OUT;

	if (MINS = '1' and HOURS = '0') then
	   if MINUTES_OUT = 59 then
	      MINUTES_OUT <= 0;
	      if HOURS_OUT = 12 then
		 HOURS_OUT <= 1;
		 AM_PM_OUT <= not AM_PM_OUT;
	      else
		 HOURS_OUT <= HOURS_OUT + 1;
	      end if;
	   else
	      MINUTES_OUT <= MINUTES_OUT + 1;
	   end if;
	elsif (HOURS = '1' and MINS = '0') then
	   if HOURS_OUT = 12 then
	      HOURS_OUT <= 1;
	      AM_PM_OUT <= not AM_PM_OUT;
	   else
	      HOURS_OUT <= HOURS_OUT + 1;
	   end if;
	end if;

   end process;

end BEHAVIOR;