--*************************************************************************
-- HDL Model : ALARM_SM_2.vhd
-- Original HDL Model : /tnfs/v3/amoor/hw1/behv/alarm_sm_2.vhd
--*************************************************************************
-- Authors and Owners : Synopsys
-- Functional Description : This block is a simple state machine that toggles the mode of the
-- alarm (whether the buzzer activated or turned off).
-- Application Intent : Alarm Clock
-- Interface Specifications :  3 single-bit inputs, 1 single-bit output.
-- Tools and Versions Used/Needed :
---- Altera Version 9.4 Synthesized: Yes
---- Altera Version number Simulated: No
---- Viewlogic Synthesized : Yes
---- FPGA Express Synthesized : No
-- Size :
---- Altera : Logic Cells= 1
----          Input Lines= 3
----          Output Lines= 1
---- Viewlogic : Cell Count= 
----             Gate Equivalent= 
----             Number of Nets= 
--*************************************************************************
--*************************************************************************
entity ALARM_SM_2 is 
	port(COMPARE_IN,TOGGLE_ON : in bit;
             CLOCK: in bit;
	     RING : out bit);
end;

architecture BEHAVIOR of ALARM_SM_2 is 
	type state_type is (IDLE, ACTIVATE);
	signal CURRENT_STATE, NEXT_STATE: state_type;
begin
	COMBIN: process(CURRENT_STATE,COMPARE_IN,TOGGLE_ON)
	begin
	case CURRENT_STATE is 
		when IDLE =>
			RING <= '0';
			if (COMPARE_IN and TOGGLE_ON) = '1' then
				NEXT_STATE <= ACTIVATE;
			else
				NEXT_STATE <= IDLE;
			end if;

		when ACTIVATE =>
			RING <= '1';
			if TOGGLE_ON = '0' then
				NEXT_STATE <= IDLE;
			else
				NEXT_STATE <= ACTIVATE;
			end if;
	end case;
	end process;

	SYNCH: process
	begin
	wait until CLOCK' event and CLOCK = '1';
	CURRENT_STATE <= NEXT_STATE;
	end process;
end BEHAVIOR;