--*************************************************************************
-- HDL Model : COMPARATOR.vhd
-- Original HDL Model : /tnfs/v3/amoor/hw1/behv/comparator.vhd
--*************************************************************************
-- Authors and Owners : Synopsys
-- Functional Description : A comparator to determine if the current time is equal to the
-- alarm time.
-- Application Intent : Alarm Clock
-- Interface Specifications :  4 integer inputs, 2 single-bit inputs, 1 single-bit output. 
-- Tools and Versions Used/Needed :
---- Altera Version 9.4 Synthesized: Yes
---- Altera Version number Simulated: No
---- Viewlogic Synthesized : Yes
---- FPGA Express Synthesized : No
-- Size :
---- Altera : Logic Cells= 7
----          Input Lines= 22
----          Output Lines= 1
---- Viewlogic : Cell Count= 
----             Gate Equivalent= 
----             Number of Nets= 
--*************************************************************************
--*************************************************************************
entity COMPARATOR is
    port (ALARM_HRS,CLOCK_HRS :in  INTEGER range 1 to 12; 
          ALARM_MINS,CLOCK_MINS : in  INTEGER range 0 to 59;
	  ALARM_AM_PM, CLOCK_AM_PM: in BIT;
	  RINGER: out BIT);
end;

architecture BEHAVIOR of COMPARATOR is
begin

   COMP:process(ALARM_HRS,CLOCK_HRS,ALARM_MINS,CLOCK_MINS,ALARM_AM_PM,CLOCK_AM_PM)
   begin
	RINGER <= '0';
	if ((ALARM_HRS = CLOCK_HRS) and (ALARM_MINS = CLOCK_MINS) and 
           (ALARM_AM_PM = CLOCK_AM_PM))  then
		RINGER <= '1';
	 end if;

   end process;

end BEHAVIOR;