--*************************************************************************
-- HDL Model : HOURS_FILTER.vhd
-- Original HDL Model : /tnfs/v3/amoor/hw1/behv/hours_filter.vhd
--*************************************************************************
-- Authors and Owners : Synopsys
-- Functional Description : This block filters out the tens digit the hour value passed to it.
-- Application Intent : Alarm Clock
-- Interface Specifications : 1 7-bit bit_vector input, 1 7-bit bit_vector output.
-- Tools and Versions Used/Needed :
---- Altera Version 9.4 Synthesized: Yes
---- Altera Version number Simulated: No
---- Viewlogic Synthesized : Yes
---- FPGA Express Synthesized : No
-- Size :
---- Altera : Logic Cells= 9
----          Input Lines= 7
----          Output Lines= 7
---- Viewlogic : Cell Count= 
----             Gate Equivalent= 
----             Number of Nets= 
--*************************************************************************
--*************************************************************************
entity HOURS_FILTER is
    port (TENS_DIGIT_HOURS_IN : in BIT_VECTOR (6 downto 0);
	  TENS_DIGIT_HOURS_OUT : out BIT_VECTOR (6 downto 0));
end;

architecture BEHAVIOR of HOURS_FILTER is
begin

   process (TENS_DIGIT_HOURS_IN)
   begin
     if TENS_DIGIT_HOURS_IN = "1111110" then
	TENS_DIGIT_HOURS_OUT <= "0000000";
     else
	TENS_DIGIT_HOURS_OUT <= TENS_DIGIT_HOURS_IN;
     end if;
   end process;

end BEHAVIOR;