--*************************************************************************
-- HDL Model : TIME_BLOCK.vhd
-- Original HDL Model : /tnfs/v3/amoor/hw1/behv/time_block.vhd
--*************************************************************************
-- Authors and Owners : Synopsys
-- Functional Description : This is a higher-level block that connects parts of the time-keeping system.
-- Application Intent : Alarm Clock
-- Interface Specifications :  4 single-bit inputs, 2 buffered integer I/O, 1 buffered single-bit I/O.
-- Tools and Versions Used/Needed :
---- Altera Version 9.4 Synthesized: Yes
---- Altera Version number Simulated: No
---- Viewlogic Synthesized : Yes
---- FPGA Express Synthesized : No
-- Size :
---- Altera : Logic Cells= 68
----          Input Lines= 4
----          Output Lines= 11
---- Viewlogic : Cell Count= 
----             Gate Equivalent= 
----             Number of Nets= 
--*************************************************************************
--*************************************************************************
entity TIME_BLOCK is
	port (SET_TIME,HRS,MINS,CLK : in BIT;
	      CONNECT6 : buffer INTEGER range 1 to 12;
	      CONNECT7 : buffer INTEGER range 0 to 59;
	      CONNECT8 : buffer BIT);
end;

architecture BEHAVIOR of TIME_BLOCK is
	component TIME_STATE_MACHINE
	port(TIME_BUTTON: in BIT;
	     HOURS_BUTTON: in BIT;
	     MINUTES_BUTTON: in BIT;
	     CLK: in BIT;
	     SECS: out BIT;
	     HOURS: out BIT;
	     MINS: out BIT);
	end component;

	component  TIME_COUNTER 
	port(SECS: in BIT;
	     HOURS: in BIT;
	     MINS: in BIT;
	     CLK: in BIT;
	     HOURS_OUT: buffer INTEGER range 1 to 12;
	     MINUTES_OUT: buffer INTEGER range 0 to 59;
	     AM_PM_OUT: buffer BIT);
	end component;

-- Top level nets that connect major modules 

	signal CONNECT3,CONNECT4,CONNECT5 : BIT;

	begin
		U1:  TIME_STATE_MACHINE port map(SET_TIME,HRS,MINS,CLK,CONNECT5,CONNECT3,CONNECT4);

		U2: TIME_COUNTER port map (CONNECT5, CONNECT3,CONNECT4,CLK,CONNECT6,CONNECT7,CONNECT8);

end;