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TOP | |
| Altered Filename TOP.vhd |
Orginal Filename /tnfs/v3/amoor/hw1/behv/top.vhd |
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Description : | |
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Authors and Owners | |
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Synopsys | |
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Functional Description | |
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This is the toplevel interconnection block. All the | |
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Testing : | |
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Altera Version 9.4 Synthesized : Yes Altera Version number Simulated : No Viewlogic Synthesized : Yes FPGA Express Synthesized : No | |
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Results : | |
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Altera Synthesis Report File Simulation Vector Test File Simulation Results Table Logic Cells= 68 | |