--*************************************************************************
-- HDL Model : TOP.vhd
-- Original HDL Model : /tnfs/v3/amoor/hw1/behv/top.vhd
--*************************************************************************
-- Authors and Owners : Synopsys
-- Functional Description : This is the top-level interconnection block.  All the 
-- other modules are connected to each other based on this file.  All external 
-- interfaces (buttons, display, buzzer, etc.) are also routed through this level.
-- Application Intent : Alarm Clock
-- Interface Specifications :  6 single-bit inputs, 2 single-bit outputs, 2 14-bit bit_vector outputs.
-- Tools and Versions Used/Needed :
---- Altera Version 9.4 Synthesized: Yes
---- Altera Version number Simulated: No
---- Viewlogic Synthesized : Yes
---- FPGA Express Synthesized : No
-- Size :
---- Altera : Logic Cells= 7
----          Input Lines= 4
----          Output Lines= 3
---- Viewlogic : Cell Count= 
----             Gate Equivalent= 
----             Number of Nets= 
--*************************************************************************
--*************************************************************************
use work.synopsys.all;

entity TOP is
	port(TOGGLE_SWITCH,SET_TIME,ALARM,HRS,MINS,CLK :in BIT;
             SPEAKER_OUT :out BIT; 
	     AM_PM_DISPLAY :out BIT;
	     DISP1,DISP2:out BIT_VECTOR(13 downto 0));
end;

architecture BEHAVIOR of TOP is 

	component TIME_BLOCK 
	port(SET_TIME,HRS,MINS,CLK: in BIT;
	     CONNECT6:buffer INTEGER range 1 to 12;
	     CONNECT7:buffer INTEGER range 0 to 59;
	     CONNECT8: buffer BIT); 
	end component;

	component  ALARM_BLOCK
	port(ALARM,HRS,MINS,CLK: in BIT;
	     CONNECT9: buffer INTEGER range 1 to 12;
             CONNECT10: buffer INTEGER range 0 to 59;
	     CONNECT11: buffer BIT); 
	end component;

	component CONVERTOR_CKT
 	port (connect13 : in unsigned(9 downto 0);
              disp1,disp2 : out BIT_VECTOR(13 downto 0));
	end component;

	component  COMPARATOR 
	port(ALARM_HRS,CLOCK_HRS:in  INTEGER range 1 to 12;
	     ALARM_MINS,CLOCK_MINS:in  INTEGER range 0 to 59;
	     ALARM_AM_PM,CLOCK_AM_PM:in BIT; 
 	     RINGER:out BIT); 
	end component;

	component ALARM_SM_2
	port(COMPARE_IN,TOGGLE_ON: in BIT; 
	     CLOCK:in BIT;
	     RING: out BIT); 
	end component;

	component MUX
	port(ALARM_HRS:in  INTEGER range 1 to 12;
	     ALARM_MINS	:in  INTEGER range 0 to 59;
	     ALARM_AM_PM: in BIT; 
	     TIME_HRS:in  INTEGER range 1 to 12;
	     TIME_MINS:in  INTEGER range 0 to 59;
	     TIME_AM_PM	: in BIT; 
             ALARM_SET: in BIT;
	     OUTBUS: out unsigned(10 downto 0));
	end component;

--Top level nets that connect major modules

	signal KONNECT7,KONNECT10 : INTEGER range 0 to 59; 
	signal KONNECT8,KONNECT11,KONNECT12 : BIT; 
	signal KONNECT6,KONNECT9 : INTEGER range 1 to 12; 
	signal KONNECT13 : unsigned(10 downto 0);

	begin
		AM_PM_DISPLAY <= KONNECT13(0);

		U1: TIME_BLOCK port map(SET_TIME,HRS,MINS,CLK,KONNECT6,KONNECT7,KONNECT8);

		U2: ALARM_BLOCK port map(ALARM,HRS,MINS,CLK,KONNECT9,KONNECT10,KONNECT11);

		U3: CONVERTOR_CKT port map(KONNECT13(10 downto 1),DISP1,DISP2);

		U4: COMPARATOR port map(KONNECT9,KONNECT6,KONNECT10,KONNECT7,KONNECT11,KONNECT8,KONNECT12);

		U5: ALARM_SM_2 port map(KONNECT12,TOGGLE_SWITCH,CLK,SPEAKER_OUT);

		U6: MUX port map(KONNECT9,KONNECT10,KONNECT11,KONNECT6,KONNECT7,KONNECT8,ALARM,KONNECT13);

	end;