Physical Design
Firstly, a single-row layout of the comparator cell was generated manually in Magic with the basic cells provided by EECS Department of University of California, Berkeley. The basic cells were edited to meet the requirement in this project; e.g. height of 50 lambda, and size of transistors Wp=9 and Wn=3. The comparator bit-slice is shown in Figure 15 with the size of 608 x 50 lambda. The layout was extracted and a switch-level simulation was executed with IRSIM as shown in Figure 16. The switch level simulation is similar to the one generated in Viewsim.
From IRSIM time simulator for bit-slice comparator, the rising time delay for the output is 1.7ns, while the falling time delay for the output is 1.4ns. The time needed from input A and B to the output AGTBINV is 2.3ns.
After the single-row layout was done, the bit-slice was replicated to generate 4-bit comparator cell as shown in Figure 17 and Figure 18.This will allow 4-bit input A and B, and give result in 4-bit output AEQB and AGTBINV. AEQBIN and AGTBININV are functioned as the control line which run vertically.
The 4-bit comparator was then extracted and simulated with IRSIM. The first simulation as shown in Figure 19 with no load condition. The delay occurs from inputs A and B to the output AGTBINV is 2.3ns.
The Figure 20 shows the switch-level simulation from IRSIM with 8 load condition; i.e. 8-inverter connected in parallel. This load was connected to the most significant bit of one of the output which is AEQBINV[3]. The delay for the circuit with 8-load condition from inputs A and B to the output AGTBINV is 2.7ns.
As in Standard Cell Development, the Datapath was also simulated for the switch-level using SPICE. Switch-level simulation for one bit-slice comparator was successfully performed, which result in information of rising time delay for the output is 1.9ns and falling time delay is 1.2ns (see Figure 21).
However, a problem was encountered when simulating for 4-bit comparator. A .spice file was generated when the layout was extracted for simulation with SPICE. This file was then modified by adding commands and the spice models. During simulation, spice displayed a message saying that iteration limit was reached.
A command .OPTION .ITL4 = ## was added to solve the problem with ## was number greater than the default value which is 10. However, this did not seem to solve the problem even though different values had been tried.
SPICE simulated was terminated to continue the project to the next step : Framing.